The present invention relates in general to integrated circuit memories, and in particular to a method and circuit for providing fast equilibration of complementary data lines following a write cycle.
In both dynamic and static random access memory circuits, a memory read operation relies on the ability to sense a small differential voltage across a complementary pair of input/output (I/O) data lines. To minimize read access time from memory cell selection to differential signal generation, the lines must be equilibrated before cell selection. While a read operation causes a voltage differential of typically a few hundred millivolts across the I/O data lines, a write operation causes a full logic level differential voltage (i.e., the power supply voltage of 3 to 5 volts). Because the differential voltage on the I/O data lines is much larger in the case of a write operation, equilibration of the I/O data lines after a write cycle requires a longer time compared to the time required for equilibration after a read cycle. The operation of the memory circuit thus slows down when performing a read cycle immediately following a write cycle.
Consider the I/O data path for a typical dynamic random access memory (DRAM) shown in FIG. 1. Memory cells 100 are located at the cross section of word (or row) lines 102 and bit (or column) lines 104. To read the contents of a given memory cell 100, the memory circuit receives address information corresponding to the location of that memory cell. Upon decoding the address information, the word line connecting to the cell is selected and the memory cell is accessed. At this time a charge storage element 106 in memory cell 100 couples to the associated bit line causing charge sharing to occur between the charge storage element 106 and the parasitic capacitance on bit line 104. A sense amplifier 105 connecting to the selected bit line and it's complement detects the resulting voltage differential and amplifies the signal to full logic levels (i.e. ground and power supply voltage). Thus, at the completion of the sensing operation, opposite polarity logic levels develop on the pair of bit lines.
In DRAM circuits, a pair of complementary I/O data lines 108 typically connect to numerous column lines 104 via column decode transistors 110. To connect the column line with the accessed memory cell to I/O data lines 108, the respective column decode transistors 110 are activated. The complementary bit lines then connect to the complementary pair of I/O data lines 108 allowing the information to be transferred from the bit lines onto I/O data lines 108 in a read cycle, or from the I/O lines onto the bit lines in a write cycle. In a read cycle, a differential sense amplifier 112 receives complementary I/0 data lines 108 at its inputs and generates the output data at its output. Before connecting to the bit lines, I/O data lines 108 are charged to an equal voltage. This is typically accomplished by a pair of PMOS pull-up transistors 114C and 114T connecting each I/O data line to the positive supply voltage VDD. For the purpose of this description, it is assumed that both PMOS pull-up transistors 114C and 114T remain on during read cycle. Once the column decode signal is asserted and the bit lines connect to I/O data lines 108, approximately 1 mA of current flows through the pull-up PMOS transistor 114 that connects to the low going I/O data line. With an effective resistance for PMOS pull-up transistor 114 of a few hundred ohms, the current causes a voltage drop of a few hundred millivolts below VDD on the low going I/O data line. The complementary I/O data line remains at VDD. This differential voltage is then sensed and amplified by differential sense amplifier 112 to generate the output data.
To read the contents of another memory cell 100 (in the same row but a different column) following a first read cycle, there must therefore be enough time allowed for I/O data lines 108 to equilibrate. This will require a relatively short time delay since after a read operation, the I/O data lines are only a few hundred millivolts (e.g. 400 my) apart. To read the contents of a memory cell 100 immediately after a write cycle, however, data line equilibration requires a significantly longer time delay. This is due to the fact that the write cycle brings the potential on complementary I/O data lines 108 to full logic levels (i.e., ground and VDD). When writing a logical "0" NMOS pull-down transistor ll6T is turned on to connect the true data line 108 to ground, while PMOS pull-up transistor ll4T is turned off to disconnect the true data line from VDD. The NMOS pull-down transistor 116C remains off and the PMOS pull-up transistor 114C remains on for the complementary data line. When writing a logical "1" NMOS pull-down transistor 116C is on to connect the complementary data line to ground while PMOS pull-up transistor 114C is turned off to disconnect this line from VDD. In this case, the NMOS pull-down transistor 116T remains off and the PMOS pull-up transistor 114T remains on for the true data line. When an array is selected, at all times except when writing, both PMOS transistors 114 are turned on and both NMOS pull-down transistors 116 are turned off to pull both I/O data lines 108 up to VDD (in the absence of read current). Thus, to equilibrate the voltage on the I/O data lines for a read cycle after a write cycle, the data line carrying a logic low signal must be pulled up several volts (typically 3 to 5 volts) instead of a few hundred millivolts.
FIG. 2 is a timing diagram showing the voltage on the I/O data lines for memory read and write cycles. The column decode signal is shown by signal 2A defining the timing of a read or write cycle. Signal 2B shows the voltage on the I/O data lines during a read cycle, while signal 2C shows the voltage on the I/O data lines during a write cycle. As can be seen from the diagram, a read operation can start at time t.sub.1 (signal 2B) when the data lines have equilibrated after a read cycle. After a write cycle, however, because the voltage differential is much greater, a read operation can not occur until a considerably later time t.sub.3 (signal 2C) when equilibration occurs.
A similar problem exists in the case of static random access memory (SRAM) circuits. Data input and output typically take place on the same set of data lines. The circuit for an SRAM is similar to that shown in FIG. 1 without the memory cells 100, if one considers sense amplifier 105 as the SRAM memory cell flip flop, decode transistors 110 as SRAM cell access transistors, and I/O data lines 108 as SRAM bit lines. There is therefore an identical equilibration delay problem for a read cycle immediately following a write cycle in the case of an SRAM.
Existing memory circuits therefore suffer from an additional delay when a read operation takes place immediately after a write operation. This problem would be avoided if the I/O data lines were not shared and the input and output paths were separate. However, because separate I/O paths would significantly increase the circuit area, the I/O paths are commonly not separated.
One way to reduce the equilibration delay is to reduce the effective resistance value of the PMOS pull-up transistors 114. This reduces the RC time constant and speeds up the recovery of the low I/O data line. However, smaller resistance reduces the voltage differential that develops between the complementary data lines during a read cycle. For proper operation, the differential amplifier requires a minimum .DELTA.V at its inputs. Given smaller effective pull-up resistance, to obtain a sufficiently large .DELTA.V would require larger read currents. To obtain larger read currents, column decode transistors 110 must be made larger. Larger decode transistors 110, however, directly add to the parasitic capacitance on I/O data lines 108, causing the RC time constant to increase. This is therefore not a viable option.
A modification to this approach uses large (low resistance) pull-up transistors for moderately fast equilibration, and turns off these transistors during the following read cycle. This approach, however, uses significant area for the large transistors and requires very critical timing for turning off the large pull-up transistors.
A much better approach to reducing the data line equilibration delay requires the addition of an NMOS equilibration transistor 118 that shorts the two data lines together when turned on. When the complementary data lines are shorted together, current flows through equilibration transistor 118, moving the voltage on the high data line down toward the recovering low data line while at the same time speeding up the recovery of the low data line. When the voltage on the recovering low data line reaches a high enough value such that the gate-to-source voltage of NMOS equilibration transistor 118 goes below a threshold voltage, equilibration transistor 118 turns itself off (even though its gate is still at VDD), at which point both data lines move toward VDD independently. Equilibration transistor 118 therefore turns off in time to avoid any interference with the differential voltage that will develop across the data lines due to the read operation. Equilibration transistor 118 can thus be large to obtain fast equilibration. This significantly reduces the equilibration delay since the voltage on the low data line rises faster while the voltage on the high data line drops somewhat toward the voltage on the low data line. This is illustrated by signal 2D of FIG. 2 which shows the voltage on the I/O line moving toward the voltage on the I/O line to equilibrate at time t.sub.2, earlier than time t.sub.3. However, there still remains a small differential voltage between the I/O lines throughout their exponential rise toward VDD. Thus, this reduction in the data line equilibration delay is still not enough for very high speed operation.
There is therefore a need for a faster data line equilibration technique following a write cycle in memory circuits.